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TA1318N 2003-02-19 1 toshiba bipolar linear integrated circuit silicon monolithic TA1318N sync processor, frequency counter ic for tv component signals TA1318N is a sync processor for tv component signals. TA1318N provides sync and frequency counter processing for external input signals. these functions are integrated in a 24 pin dual-in-line shrink-type plastic package. TA1318N provides i 2 c bus interface, so various functions and controls are adjustable via the bus. features ? horizontal synchronization circuit (15.75 khz, 31.5 khz, 33.75 khz, 45 khz) ? vertical synchronization circuit (525i, 525p, 625i, 750p, 1125i, 1125p, pal 100 hz, ntsc 120 hz) ? horizontal and vertical frequency counter ? horizontal pll ? accepts 2-level and 3-level sync ? accepts both negative and positive hd and vd ? clamp pulse output ? hd, vd output (polarity inverter) ? separated sync output ? mask for the copy guard signal weight: 1.22 g (typ.)
TA1318N 2003-02-19 2 block diagram 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 dac3 sw inv sw inv sw sync sepa dac1 sw sync sepa inv sw inv sw i 2 cbus decoder dv2-out sw dv1-out sw hd2-out sw hd1-out sw v-input sw h/v- freq counter v-freq det sw dac2 sw h-freq det sw v integral h-input sw v c/d v-freq sw clamp pulse hd polarity h-afc hvco cp sw h-freq sw 2 f h h-ramp h c/d test dac3 dac1 v-sync dac2 h/c- synk dac3 vd2-out vd1-out sync1-in dac1 sync2-in address sw scl sda hd2-out digital gnd hd1-out hd2-in vd2-in hd1-in vd1-in analog gnd afc filter hvco v cc dac2 vd3-in hd3-in cp-out
TA1318N 2003-02-19 3 pin functions pin no. pin name function interface circuit input signal/output signal 1 hd2-in inputs horizontal sync signal. accepts input of both positive and negative polarity. input signal from this pin is not synchronized. or 2 vd2-in inputs vertical sync signal. accepts input of both positive and negative polarity. input signal from this pin is not synchronized. or 8 1 5 1 k ? 50 k ? 8 2 5 1 k ? 45 k ? th: 0.7 v th: 0.7 v th: 0.7 v th: 0.7 v
TA1318N 2003-02-19 4 pin no. pin name function interface circuit input signal/output signal 3 hd1-in inputs horizontal sync signal. accepts input of both positive and negative polarity. input signal from this pin is not synchronized. or 4 vd1-in inputs vertical sync signal. accepts input of both positive and negative polarity. input signal from this pin is not synchronized. or 5 analog gnd gnd pin for analog circuit blocks. ? ? 8 3 5 1 k ? 50 k ? 8 4 5 1 k ? 45 k ? th: 0.7 v th: 0.7 v th: 0.7 v th: 0.7 v
TA1318N 2003-02-19 5 pin no. pin name function interface circuit input signal/output signal 6 afc filter connects filter for horizontal afc. voltage on this pin determines horizontal output frequency. dc 7 hvco connects ceramic oscillator for horizontal oscillation. use murata csbla503keczf30. ? 8 v cc vcc pin. connects 9 v (typ.). ? ? 8 6 5 300 ? 30 k ? 8 7 5 4 k ? 1 k ? 2 k ? 1 k ? 10 k ?
TA1318N 2003-02-19 6 pin no. pin name function interface circuit input signal/output signal 9 dac2 (h/c. sync output) dac2 output pin. in test mode, outputs hd or composite sync signal to frequency counter. to improve the driving ability, it is possible to connect a resister (minimum: 2 k ? ) between this pin and gnd. however, when the resister is added, the output dc voltage is down. dc or h/c sync 10 vd3-in inputs vertical sync signal. accepts input of both positive and negative polarity. or 11 hd3-in inputs horizontal sync signal. accepts input of both positive and negative polarity. or 8 11 5 1 k ? 50 k ? 8 10 5 1 k ? 45 k ? 7 v 0 v th: 0.7 v th: 0.7 v th: 0.7 v th: 0.7 v 30 k ? 8 9 14 200 ? 500 ?
TA1318N 2003-02-19 7 pin no. pin name function interface circuit input signal/output signal 12 cp-out clamp pulse (cp) output pin. outputs cp generated by sync circuit. 13 hd1-out hd output pin. open collector output. hd1/hd2 input signal is output from this pin without synchronization. polarity is switched by bus write function. or 14 digital gnd gnd pin for logic blocks. ? ? 8 13 14 200 ? 2.5 k ? 8 12 14 200 ? 500 ? 5.0 v 0 v
TA1318N 2003-02-19 8 pin no. pin name function interface circuit input signal/output signal 15 hd2-out hd output pin. open collector output. hd1/hd2 input signal is output from this pin without synchronization. polarity is switched by bus write function. or 16 sda sda pin for i 2 c bus. ? 8 15 14 200 ? 8 16 14 20 k ? 5 50 ? ack sda 4 v f
TA1318N 2003-02-19 9 pin no. pin name function interface circuit input signal/output signal 17 scl scl pin for i 2 c bus. ? 18 address sw slave address switch pin. when this pin is connected to v cc (gnd), used for dc/dd h (d8/d9 h ); when left open, da/db h . da/db dc/dd 9 v 7.5 v d8/d9 1.5 v 0 v 8 17 20 k ? 5 scl 4 v f 100 k ? 100 k ? 8 18 100 k ? 1 k ? 5 15 k ? 15 k ? 60 k ? 1.5 v 7.5 v
TA1318N 2003-02-19 10 pin no. pin name function interface circuit input signal/output signal 19 sync2-in inputs y signal (note 1) for sync separation circuit. input via clamp capacitor. white 100 = 1 v p ? p or 20 dac1 (v sync output) dac1 output pin. in test mode, outputs vd or composite sync signal to frequency counter. to improve the driving ability, it is possible to connect a resister (minimum: 2 k ? ) between this pin and gnd. however, when the resister is added, the output dc voltage is down. dc or v sync note 1: the signal format for sync1-in (pin 21) and sync2-in (pin 19) ntsc (525i/60 hz), pal/secam (625i/50 hz), ntsc double scan (525i/120 hz), pal/secam double scan (625i/100 hz), 525p/60 hz, 75 0p/60 hz, 1125i/60 hz, 1125p/30 hz this ic doesn?t have the sync-separation circuit for non-standard signals like weak strength signal, ghost signal and so on. 7 v 0 v 30 k ? 8 20 14 200 ? 500 ? 1 k ? 4 v f 1 k ? 8 19 1 k ? 5 1 k ?
TA1318N 2003-02-19 11 pin no. pin name function interface circuit input signal/output signal 21 sync1-in inputs y signal (note 1) for sync separation circuit. input via clamp capacitor. white 100 = 1 v p ? p or 22 vd1-out vd output pin. open collector output. vd1/vd2 input signal is output from this pin without synchronization. polarity is switched by bus write function. (note) when hd phase will be changed, synchronized vd width will change. use the start phase of vd. or note 1: the signal format for sync1-in (pin 21) and sync2-in (pin 19) ntsc (525i/60 hz), pal/secam (625i/50 hz), ntsc double scan (525i/120 hz), pal/secam double scan (625i/100 hz), 525p/60 hz, 75 0p/60 hz, 1125i/60 hz, 1125p/30 hz this ic doesn?t have the sync-separation circuit for non-standard signals like weak strength signal, ghost signal and so on. 8 22 14 200 ? 1 k ? 4 v f 1 k ? 8 21 1 k ? 5 1 k ? start phase start phase
TA1318N 2003-02-19 12 pin no. pin name function interface circuit input signal/output signal 23 vd2-out vd output pin. open collector output. vd1/vd2 input signal is output from this pin without synchronization. polarity is switched by bus write function. (note) when hd phase will be changed, synchronized vd width will change. use the start phase of vd. or 24 dac3 dac3 output pin. open collector output. in test mode, outputs test pulse for shipping. dc or test pulse for shipping 8 23 14 200 ? 8 24 14 500 ? start phase start phase
TA1318N 2003-02-19 13 bus control map write mode slave address: d8/da/dc h preset sub-add d7 msb d6 d5 d4 d3 d2 d1 d0 lsb msb lsb 00 h-frequency hd1/vd1-out sw hd2/vd2-out sw sepa level 1000 0000 01 dac1 dac2 dac3 test hd1-inv hd2-inv 1000 0000 02 v-frequency clp-phs freq det sw input sw 1000 0000 03 hd phase vd1-inv vd2-inv 1000 0000 read mode slave address: d9/db/dd h d7 msb d6 d5 d4 d3 d2 d1 d0 lsb 0 por v frequency det 1 hd-in h frequency det bus control functions write mode ( * : preset) ? h-frequency (horizontal oscillation frequency) switches horizontal frequency. (00): 15.75 khz (01): 31.5 khz * (10): 33.75 khz (11): 45 khz ? hd1/vd1-out sw (hd1/vd1 output switch) switches output from pin 13/22. when set to 00, 01, or 10, outputs hd/vd without synchronization. when set to 11, outputs hd/vd from the sync circuit. (note) synchronized vd width will change, when hd phase will be changed. * (00): hd1/vd1 (01): hd2/vd2 (10): hd3/vd3 (11): synchronized hd/vd ? hd2/vd2-out sw (hd2/vd2 output switch) switches output from pin 15/23. when set to 00, 01, or 10, outputs hd/vd without synchronization. when set to 11, outputs hd/vd from the sync circuit. * (00): hd1/vd1 (01): hd2/vd2 (10): hd3/vd3 (11): synchronized hd/vd ? sepa level (sync separation level switch) switches sync separation level of pin 19/21. set values are the levels from sync tip. sync separation level is changed according to the ratio of h-sync width during 1h period. * (00): 10ire (01): 15ire (10): 20ire (11): 25ire (at 1125i/60) ? dac1 (dac1 control) controls 2-bit dac (pin 9). (00): 1 v (01): 3 v * (10): 5 v (11): 7 v ? dac2 (dac2 control) controls 2-bit dac (pin 20). * (00): 1 v (01): 3 v (10): 5 v (11): 7 v ? dac3 (dac3 control) controls open collector 1-bit dac (pin 24). * (0): open (high) (1): on (low) ? test (test mode) switches dac1, 2, and 3 outputs. also used to test ic for shipping. * (0) : dac outputs are used as dac. (1): dac1 outputs v. sync to the frequency counter. dac2 outputs h. sync or c. sync to the frequency counter. dac3 outputs ic test pulse for shipping.
TA1318N 2003-02-19 14 ? hd1-inv (hd1 output polarity switch) switches hd1 output (pin 13) polarity. when set to 0, positive hd input is output as negative hd. when set to 0, output from the sync circuit is output as negative hd. * (0): normal (1): inverse ? hd2-inv (hd2 output polarity switch) switches hd1 output (pin 15) polarity. when set to 0, positive hd input is output as negative hd. when set to 0, output from the sync circuit is output as negative hd. * (0): normal (1): inverse ? v-frequency (vertical frequency switch (pull-in range)) sets vertical frequency pull-in range, vd-stop, or free-running frequency. free-running frequency is controlled by h-frequency. pull-in range format/h (v) frequency * (000 ) 48~1281 h 1125p/30 hz (33.75 khz) (001) 48~849 h 750p/60 hz (45 khz) (010) free-run free-running frequency is controlled by h-frequency. (00): 262 h (01): 525 h (10): 562 h (11): 750 h (011) 48~637 h 1125i/60 hz (33.75 khz) (100) 48~613 h 525p/60 hz (31.5 khz) (101) 48~363 h pal/secam/50 hz (15.625 khz) pal/secam double scan/100 hz (31.5 khz) (110) 48~307 h ntsc/60 hz (15.734 khz) ntsc double scan /120 hz (31.5 khz) (111) vp stop vd output is high ? clp phs (clamp pulse phase switch) switches clamp pulse phase. if no signal input, 0.9 s pulse is output from the h-c/d circuit. *(0): 1 s (3.4%) delay following hd stop phase, 0.8 s (2.7%) pulse (1): 0.5 s (1.7%) delay following hd stop phase, 0.8 s (2.7%) pulse ? freq det sw (horizontal/vertical frequency counter switch) switches input signal used for horizontal/vertical frequency counter. this switch is controlled independently from input sw. the detection result is output as read bus data. *(00): sync1 input (01): sync2 input (10)/(11): hd3/vd3 inputs ? input sw (input signal switch for synchronization) switches input signal used for synchronization. * (00): sync1 input (01): sync2 input (10)/(11): hd3/vd3 inputs ? hd phase (hd phase adjustment) adjusts phase of hd output from the sync circuit. the phase of the adjustment center value is the same as that of input h-sync or input hd. (note) synchronized vd width will change, when hd phase will be changed. (000000) : ? 5% (h periodically) *(100000) : 0% (111111) : 5% ? vd1-inv (vd1 output polarity switch) switches vd1 output (pin 22) polarity. when set to 0, negative vd input is output as negative vd. when set to 0, output from the sync circuit is output as negative vd. * (0): normal (1): inverse ? vd2-inv (vd2 output polarity switch) switches vd2 output (pin 23) polarity. when set to 0, negative vd input is output as negative vd. when set to 0, output from the sync circuit is output as negative vd. * (0): normal (1): inverse
TA1318N 2003-02-19 15 read mode ? por (power on reset) (0): status read (at second data read and subsequent) (1): power on (at first data read) ? hd-in (input signal self-check result) detects hd or h-sync input signal selected by input sw. (0): no signal input (1): signal input ? v freq det (vertical frequency of sync or vd input selected by freq det sw) (0000000) (0001100): no-vd (0001101) : vicinity of 162 hz (1111110) : vicinity of 17 hz how to calculate vertical frequency (x): convert v-freq det read data into decimal and define the resulting value as y. where h-frequency is 15.75 khz/31.5 khz, z = 476.2 s where h-frequency is 33.75 khz/45 khz, z = 474.1 s vertical frequency (x) = 1 (y z) [hz] error of y is + 1, ? 0. if vertical frequency is 162 hz or more, the frequency cannot be accurately measured. time constant used to separate v.sync from integrated c.sync is 9 s (error: 1 s). ? h freq det (horizontal frequency of sync or hd input selected by freq det sw) (0000000): no signal input (1111110): 53 khz or more how to calculate horizontal frequency (x): x, y, and z are defined same as for v freq. horizontal frequency (x) = y (5 z) [khz] error of y is + 1, ? 0. if horizontal frequency is 53 khz or more, the frequency cannot be accurately measured. when v-sync or vd is not input, horizontal frequency cannot be measured, resulting in data = (0000000). note 1: the start trigger for frequency counting is the internal reset-pulse made from ack of 2nd byte in bus read mode. the counting period is between the first v-sync (vd) and the second v-sync (vd) after the trigger. the counted data will have + 1 or ? 0 error according to the read timing. to assume stable data reading; 1. set bus reading interval more than 60 ms. 2. don?t use the first data because it is unsettled. are recommended. note 2: ignore data (1111111). this data may be obtained in case the trigger pulse and the v-sync (vd) are simultaneous. decision algorithm (detection range, detection times and so on) should be determined under consideration of note 1, note 2 and the other factors such as signal strength, existence of ghost signal, h-afc stability, i 2 c bus data transmission and so on via prototype tv set evaluation. read timing v-sync or vd more than 60 ms counting period 1 (to data 1) counting period 2 (to data 2) start trigger 1 data 1 and start trigger 2 data 2 and start trigger 3
TA1318N 2003-02-19 16 data transfer format via i 2 c bus slave address: d8/da/dc h a6 a5 a4 a3 a2 a1 a0 w/r 1 1 0 1 1 0/1 0/1 0/1 start and stop condition bit transfer acknowledge sda by transmitter only bit 9: low impedance clock pulse for acknowledgment s bit 9: high impedance 1 8 9 sda by receiver scl from master sda scl s start condition p stop condition sda scl sda stable change of sda allowed
TA1318N 2003-02-19 17 data transmit format 1 data transmit format 2 data receive format at the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave transmitter. this acknowledge is still generated by this slave. the stop condition is generated by the master. ( * important) the data read from this ic should always be completed in whole two words, not one word, otherwise the iicbus may cause error. optional data transmit format: automatic increment mode in this transmission method, data is set on automatically incremented sub-address from the specified sub-address. purchase of toshiba i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. s slave address 0 a transmit data a sub address a p 7 bit msb s: start condition 8 bit msb a: acknowledge 8 bit msb p: stop condition s slave address 0 a transmit data a sub address a transmit data n a sub address a p ?????? ?????? s slave address 1 a received data 2 a received data 1 a p 7 bit msb 8 bit msb s slave address a transmit data 2 ???? transmit data 1 a p 7 bit msb 8 bit msb 0 sub address 7 bit msb a 1 8 bit msb
TA1318N 2003-02-19 18 maximum ratings (ta = = = = 25c) characteristics symbol rating unit supply voltage v ccmax 12 v input pin signal voltage e inmax 9 v p-p power dissipation p d ( * 1) 1250 mw power dissipation reduction rate 1/qja ? 10 mw/ c operating temperature t opr ? 20~65 c storage temperature t stg ? 55~150 c note: refer to the figure below. operating condition characteristics description min typ. max unit power supply voltage (v cc ) pin 8 8.5 9.0 9.5 v hd1, hd2, hd3 input level pin 3, 1, 11 2.0 5.0 9.0 vd1, vd2, vd3 input level pin 4, 2, 10 2.0 5.0 9.0 v p-p synchronization pin 11 0.02 ? 0.20 h hd3 input width frequency detection pin 11 0.45 s ? 0.25h ? synchronization pin 10 1 s ? 47h ? vd3 input width frequency detection pin 10 1 ? 400 s sync1, sync2 input level pin 21, 19, white 100% with negative sync 0.9 1.0 1.1 v p-p hd1, hd2, vd1, vd2-out input current pin 13, 15, 22, 23 ? 0.9 1.5 dac3 input current pin 24 ? 0.5 1.0 ma d8/d9 h 0 0 1.0 address switching voltage pin 18 dc/dd h 8.0 9.0 9.0 v ambient temperature ta (c) power consumption reduction ratio p d (mw) 0 150 25 65 0 850 1250 figure p d - ta curve 10 mw/c
TA1318N 2003-02-19 19 electrical characteristics (v cc = = = = 9 v, ta = = = = 25c, unless otherwise specified) current dissipation pin name symbol test circuit min typ. max unit v cc i cc ? 32 38 44 ma ac characteristics horizontal block characteristics symbol test circuit test condition min typ. max unit s 1ph ? 0.6 0.7 0.8 sync1/2 input horizontal sync phase s 2ph ? (note ha01) 0.6 0.7 0.8 s hd3 input horizontal sync phase hd 3ph ? (note ha02) 0.6 0.7 0.8 s hd- duty1 ? 61 66 71 polarity distinction active range hd- duty2 ? (note ha03) 48 53 58 % v ths10 ? 0.040 0.070 0.100 v ths11 ? 0.060 0.106 0.152 v ths12 ? 0.081 0.142 0.203 v ths13 ? 0.102 0.178 0.255 v ths20 ? 0.040 0.070 0.100 v ths21 ? 0.060 0.106 0.152 v ths22 ? 0.081 0.142 0.203 sync1 input threshold amplitude sync2 input threshold amplitude v ths23 ? (note ha04) 0.102 0.178 0.255 v p-p hd3 input threshold amplitude (synchronization block) v thhd3 ? (note ha05) 0.65 0.75 0.85 v p-p v thhd1 ? 0.65 0.75 0.85 v thhd2 ? 0.65 0.75 0.85 hd1 input threshold voltage hd2 input threshold voltage hd3 input threshold voltage (sw block) v thhd3 ? (note ha06) 0.65 0.75 0.85 v p-p ? hp0 ? ? 2.86 3.18 3.49 ? hp0 + ? 2.86 3.18 3.49 ? hp1 ? ? 1.43 1.59 1.75 ? hp1 + ? 1.43 1.59 1.75 ? hp2 ? ? 1.33 1.48 1.63 ? hp2 + ? 1.33 1.48 1.63 ? hp3 ? ? 1.00 1.11 1.22 hd output phase adjustment variable range ? hp3 + ? (note ha07) 1.00 1.11 1.22 s cp s0 ? 0.85 1.00 1.15 cp w0 ? 0.65 0.80 0.95 s cp v0 ? 4.7 5.0 5.3 v cp s1 ? 0.35 0.50 0.65 cp w1 ? 0.65 0.80 0.95 s cp v1 ? 4.7 5.0 5.3 v cp s3 ? 0 ? 1 cp w3 ? 0.50 0.90 1.30 s clamp pulse phase/width/level cp v3 ? (note ha08) 4.7 5.0 5.3 v
TA1318N 2003-02-19 20 characteristics symbol test circuit test condition min typ. max unit delayed hd pulse width w d-hd ? (note ha09) 1.0 1.2 1.4 s v13th0 ? 4.5 5.0 5.5 v13tl0 ? ? 0.1 0.5 v13th1 ? 4.5 5.0 5.5 v13tl1 ? ? 0.1 0.5 v13th2 ? 4.5 5.0 5.5 v13tl2 ? ? 0.1 0.5 v13th3 ? 4.5 5.0 5.5 hd1 output voltage v13tl3 ? ? ? 0.1 0.5 v v15th0 ? 4.5 5.0 5.5 v15tl0 ? ? 0.1 0.5 v15th1 ? 4.5 5.0 5.5 v15tl1 ? ? 0.1 0.5 v15th2 ? 4.5 5.0 5.5 v15tl2 ? ? 0.1 0.5 v15th3 ? 4.5 5.0 5.5 hd2 output voltage v15tl3 ? ? ? 0.1 0.5 v v13ih0 ? 4.5 5.0 5.5 v13il0 ? ? 0.1 0.5 v13ih1 ? 4.5 5.0 5.5 v13il1 ? ? 0.1 0.5 v13ih2 ? 4.5 5.0 5.5 v13il2 ? ? 0.1 0.5 v13ih3 ? 4.5 5.0 5.5 hd1 output voltage (polarity inverse) v13il3 ? ? ? 0.1 0.5 v v15ih0 ? 4.5 5.0 5.5 v15il0 ? ? 0.1 0.5 v15ih1 ? 4.5 5.0 5.5 v15il1 ? ? 0.1 0.5 v15ih2 ? 4.5 5.0 5.5 v15il2 ? ? 0.1 0.5 v15ih3 ? 4.5 5.0 5.5 hd2 output voltage (polarity inverse) v15il3 ? ? ? 0.1 0.5 v id1 ? 310 385 460 id2 ? 310 385 460 id3 ? 520 650 780 afc phase detection current id4 ? (note hb01) 520 650 780 a vco oscillation start voltage v vco ? (note hb02) 3.9 4.2 4.5 v th00 ? 1.4 1.8 2.2 th01 ? 1.4 1.8 2.2 th10 ? 1.4 1.8 2.2 hd output pulse width (free-run) th11 ? (note hb03) 1.4 1.8 2.2 s
TA1318N 2003-02-19 21 characteristics symbol test circuit test condition min typ. max unit f00 ? 15.59 15.75 15.91 f01 ? 31.19 31.5 31.82 f10 ? 33.41 33.75 34.09 f11 ? 44.55 45 45.45 horizontal free-run frequency f50 ? (note hb04) 15.47 15.625 15.78 khz bh00 ? 2.4 3.0 3.6 bh01 ? 4.8 6.0 7.2 bh10 ? 4.8 6.0 7.2 horizontal oscillation control sensitivity bh10 ? (note hb05) 7.1 8.9 10.7 khz/v vdac 10 ? 0.5 1.0 1.5 vdac 11 ? 2.7 3.0 3.3 vdac 12 ? 4.7 5.0 5.3 dac1 output voltage vdac 13 ? ? 6.5 7.0 7.5 v vdac 20 ? 0.5 1.0 1.5 vdac 21 ? 2.7 3.0 3.3 vdac 22 ? 4.7 5.0 5.3 dac2 output voltage vdac 23 ? ? 6.5 7.0 7.5 v vdac 30 ? ? 0.5 0.7 dac3 output voltage vdac 31 ? ? 8.5 8.8 ? v
TA1318N 2003-02-19 22 vertical block characteristics symbol test circuit test condition min typ. max unit v thvd1 ? 0.65 0.75 0.85 v thvd2 ? 0.65 0.75 0.85 vd1 input threshold voltage vd2 input threshold voltage vd3 input threshold voltage (sw block) v thvd3 ? (note va01) 0.65 0.75 0.85 v p-p vd3 input threshold voltage (synchronization block) v thvd3 ? (note va02) 0.65 0.75 0.85 v p-p v22th0 ? 4.5 5.0 5.5 v22tl0 ? ? 0.1 0.5 v22th1 ? 4.5 5.0 5.5 v22tl1 ? ? 0.1 0.5 v22th2 ? 4.5 5.0 5.5 v22tl2 ? ? 0.1 0.5 v22th3 ? 4.5 5.0 5.5 vd1 output voltage v22tl3 ? ? ? 0.1 0.5 v v23th0 ? 4.5 5.0 5.5 v23tl0 ? ? 0.1 0.5 v23th1 ? 4.5 5.0 5.5 v23tl1 ? ? 0.1 0.5 v23th2 ? 4.5 5.0 5.5 v23tl2 ? ? 0.1 0.5 v23th3 ? 4.5 5.0 5.5 vd2 output voltage v23tl3 ? ? ? 0.1 0.5 v v22ih0 ? 4.5 5.0 5.5 v22il0 ? ? 0.1 0.5 v22ih1 ? 4.5 5.0 5.5 v22il1 ? ? 0.1 0.5 v22ih2 ? 4.5 5.0 5.5 v22il2 ? ? 0.1 0.5 v22ih3 ? 4.5 5.0 5.5 vd1 output voltage (polarity inverse) v22il3 ? ? ? 0.1 0.5 v v23ih0 ? 4.5 5.0 5.5 v23il0 ? ? 0.1 0.5 v23ih1 ? 4.5 5.0 5.5 v23il1 ? ? 0.1 0.5 v23ih2 ? 4.5 5.0 5.5 v23il2 ? ? 0.1 0.5 v23ih3 ? 4.5 5.0 5.5 vd2 output voltage (polarity inverse) v23il3 ? ? ? 0.1 0.5 v vp w0 ? 251 286 321 vp w1 ? 126 143 160 vp w2 ? 117 133 150 vertical output pulse width vp w3 ? (note va03) 88 100 112 s
TA1318N 2003-02-19 23 characteristics symbol test circuit test condition min typ. max unit fv0 ? 26.02 26.35 26.67 fv1 ? 39.21 39.75 40.30 fv3 ? 52.20 52.98 53.77 fv4 ? 54.24 55.06 55.89 fv5 ? 91.28 92.98 94.69 fv6 ? 107.8 109.9 112.1 fv20 ? 57.0 60.0 63.0 fv21 ? 57.0 60.0 63.0 fv22 ? 57.0 60.0 63.0 vertical free-run frequency fv23 ? (note va04) 57.0 60.0 63.0 hz fvpl0 ? 311 321 332 fvpl1 ? 624 643 663 fvpl2 ? 668 689 710 vertical pull-in range fvpl3 ? (note va05) 891 918 947 hz 15.75 khz ? 9.6 11.8 14.0 31.50 khz ? 5.7 6.8 7.9 33.75 khz ? 5.3 6.4 7.5 sync input-vd output phase difference 45.00 khz ? ? 4.4 5.2 6.0 s
TA1318N 2003-02-19 24 test conditions and measuring method sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) ha01 sync1/2 input horizontal sync phase c b a b b a (1) set sub-address (02) 60. (2) sw19-a and sw21-b. (3) input signal a (horizontal 33.75 khz ) to pin 21 (sync1-in). (4) set sub-address (02) 61. (5) measure the phase difference s 1ph between pin 21 and pin 6 (afc filter) wave form. (6) sw19-b and sw21-a. (7) input signal a (33.75 khz ) to pin 19 (sync2-in). (8) set sub-address (02) 01. (9) measure the phase difference s 2ph between pin 19 and pin 6 (afc filter) wave form. signal a pin 6 wave form 29.63 s s 1ph ? s 2ph 0.285 v 0.593 s
TA1318N 2003-02-19 25 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) ha02 hd3 input horizontal sync phase c b ? ? (1) set sub-address (00) 40 and (02) 82. (2) input signal b (horizontal 31.5 khz ) to pin 11 (hd3-in). (3) measure the phase difference hd 3ph between pin 11 and pin 6 (afc filter) wave form. ha03 polarity distinction active range c b ? ? (1) set sub-address (00) 70 and (02) 82. (2) input signal b ((horizontal 31.5 khz ) to pin 11 (hd3-in). (3) decreasing the duty of signal b to 0% (get negative period shorter), measure the duty of signal b (hd-duty1) when the phase between pin 11 and pin 13 (hd1-out) change. (4) increasing the duty of signal b to 100% (get negative period longer), measure the duty of signal b (hd-duty2) when the phase between pin 11 and pin 13 (hd1out) change. * duty = a/(a + b) 100 (%) signal b 31.75 s 1.5 v 2.35 s a b signal b pin 6 wave form 31.75 s hd 3ph 1.5 v 2.35 s
TA1318N 2003-02-19 26 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) ha04 sync1 input threshold amplitude sync2 input threshold amplitude c b a b b a (1) set sub-address (00) 0b and (02) 60. (2) input signal a (33.75 khz) to pin 21 (sync1-in) (3) measure the sync. tip dc voltage of signal a on pin 21 (sync1-in). (v sync11 ) (4) supply external voltage via 100 k ? to pin 21 and increase the voltage. (5) measure the sync. tip dc voltage (v sync12 ) when hd-out desynchronizes with signal a calculate v ths10 . v ths10 = v sync12 ? v sync11 (6) set sub-address (00) b1, b2 and b3 and calculate v ths11 , v ths12 and v ths13 as well. (7) calculate v ths20 , v ths21 , v ths22 and v ths23 against pin 19 (sync2-in) in the same way as 4 to 6. ha05 hd3 input threshold amplitude (synchronization block) c b ? ? (1) set sub-address (00) 70 and (02) 62. (2) input signal b (31.5 khz) to pin 11 (hd3-in). (3) increasing the voltage of signal b from 0 v, measure the voltage of signal b v thhd3 when hd1-out lock. signal a 29.63 s 0.285 v 0.593 s signal b 31.75 s v thhd1 2.35 s
TA1318N 2003-02-19 27 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) ha06 hd1 input threshold voltage hd2 input threshold voltage hd3 input threshold voltage (sw block) c b ? ? (1) set sub-address (00) 40. (2) input signal b (31.5 khz) to pin 3 (hd1-in). (3) increasing the voltage of signal b from 0 v, measure the voltage of signal b v thhd1 when hd1-out lock. (4) measure the voltage of pin 1 v thhd2 . measure the voltage of pin 11 v thhd3 as well. signal b 31.75 s v thhd1 2.35 s
TA1318N 2003-02-19 28 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) ha07 hd output phase adjustment variable range c b ? ? (1) set sub-address (00) 30. (2) input signal b (horizontal period t = 63.5 s) to pin 11 (hd3-in). (3) set sub-address (02) 02. (4) change form 00 to 7c sub-address (03), then measure the phase change quantity ( ? hp0 ? ) of pin 13 (hd1-out) wave form. (5) change form 80 to fc sub-address (03), then measure the phase change quantity ( ? hp0 + ) of pin 13 (hd1-out) wave form. (6) when horizontal period of signal b is t = 31.75 s measure ? hp1 ? and ? hp1 + as well. (7) when horizontal period of signal b is t = 29.63 s measure ? hp2 ? and ? hp2 + as well. (8) when horizontal period of signal b is t = 22.22 s measure ? hp3 ? and ? hp3 + as well. signal b t s 1.5 v 2.35 s ? hp * + ? hp * ? pin 15 wave form data (00) pin wave form data (7c) (80) pin wave form data (fc)
TA1318N 2003-02-19 29 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) ha08 clamp pulse phase/width/level c b ? ? (1) set sub-address (00) b0. (2) input signal a (horizontal 33.75 khz) to pin 11 (hd3-in). (3) set sub-address (02) 02. (4) measure the clamp pulse phase (cp s0 ), width (cp w0 ), output level (cp v0 ) of pin 12 (clp-out) against signal a. (5) set sub-address (02) 12. (6) measure the clamp pulse phase (cp s1 ), width (cp w1 ), output level (cp v1 ) of pin 12 (scp-out) against signal a. (7) input no-signal to pin 11. (8) measure the clamp pulse phase (cp s2 ), width (cp w2 ), output level (cp v2 ) of pin 12 (scp-out) against pin 13 (hd-out). signal a 29.63 s 1.5 v 2.35 s cp s3 cp w0 ? cp w1 pin 12 wave form pin 13 wave form pin 12 wave form cp s0 ? cp s1 cp v3 cp v0 ? cp v1 cp w3
TA1318N 2003-02-19 30 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) ha09 delayed hd pulse width c b ? ? (1) set sub-address (00) 70. (2) input signal b (horizontal 31.5 khz) to pin 11 (hd3-in). (3) set sub-address (02) 62. (4) measure the pulse width (wdhd) of pin 6 (afc filter) wave form. signal b pin 6 wave form 31.75 s wd-hd 1.5 v 2.35 s
TA1318N 2003-02-19 31 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) hb01 afc phase detection current open b a b (1) bus control data preset. (2) horizontal oscillation frequency is 15.75 khz (00). (3) sw6 open. measure the voltage of pin 6 v6 (no external supply). (4) connect external supply with pin 6, and supply the voltage (v6). (5) input signal (below figure) to pin 21 (sync1-in). when input sw is sync1-in , measure v1 and v2 of pin 6 wave form. (6) supply v6 ? 0.1 v and v6 + 0.1 v to pin 6, then measure v3 and v4. (7) calculate by following equations. id1 [ a] = (v1 [v] 1 [k ? ]) 1000 id2 [ a] = (v2 [v] 1 [k ? ]) 1000 id3 [ a] = (v3 [v] 1 [k ? ]) 1000 id4 [ a] = (v4 [v] 1 [k ? ]) 1000 hb02 vco oscillation start voltage ? ? ? ? (1) increasing the voltage of pin 8 v cc form 2.5v, measure the voltage v vco when pin 7 appear oscillation wave form. pin 21 wave form pin 6 wave form 63.5 s 0.25 v v1, v3 v2, v4
TA1318N 2003-02-19 32 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) hb03 hd output pulse width (free-run) c b ? ? (1) bus control data preset. (2) when horizontal oscillation frequency is 15.75 khz (00), measure the output pulse width th00 of pin 13 (hd1-out) wave form. (3) when horizontal oscillation frequency is 31.5 khz (01), 33.75 khz (10), 45 khz (11), measure the output pulse width th01, th02, th03 as well. hb04 horizontal free-run frequency open b ? ? (1) bus control data preset. (2) sw6 open. when horizontal oscillation frequency is 15.75 khz (00), measure the oscillation frequency f00 of pin 13 (hd1-out) wave form. (3) when horizontal oscillation frequency is 31.5 khz (01), 33.75 khz (10), 45 khz (11), measure the oscillation frequency f01, f10, f11 as well. (4) when horizontal oscillation frequency is 15.75 khz (00) and vertical free-run frequency is (101), measure the oscillation frequency f50 of pin 15 wave form. hb05 horizontal oscillation control sensitivity open b ? ? (1) bus control data preset. (2) sw6 open. (3) connect external voltage with pin 6 . horizontal oscillation frequency is 15.75 khz (00). supply v6 (about 6.3 v) + 0.05 v or v6 ? 0.05 v to pin 6, then measure the frequency fa, fb of pin 13 (hd1-out) wave form. calculate frequency changing ratio (bh00). bh00 = (fb ? fa)/0.1 (4) when horizontal oscillation frequency is 31.5 khz (01), 33.75 khz (10), 45 khz (11), calculate bh01, bh10, bh11 as wall. th pin 13 (hd1out) wave form
TA1318N 2003-02-19 33 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) va01 vd1 input threshold voltage vd2 input threshold voltage vd3 input threshold voltage (sw block) c b ? ? (1) set sub-address (00) 80. (2) input signal a (vertical 60 hz) to pin 4 (vd1-in). (3) set sub-address (02) 00. (4) increasing the voltage of signal a from 0 v. measure the voltage of signal b v thvd1 when vd1-out lock. (5) measure v thvd2 and v thvd3 against pin 2 and pin 10 as wall. va02 vd3 input threshold voltage (synchronization block) c b ? ? (1) set sub-address (00) 70. (2) input signal b (vertical 60 hz) to pin 10 (vd3-in). (3) set sub-address (02) 03. (4) increasing the voltage of signal b from 0 v, measure the voltage of signal a v thvd3 when vd1-out lock. 0.12 ms 16.67 ms signal a v thvd1 0.12 ms 16.67 ms signal a
TA1318N 2003-02-19 34 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) va03 vertical output pulse width c b ? ? (1) input signal a (horizontal 33.75 khz) to pin 11 (hd3-in). (2) set sub-address (02) 02. (3) when sub-addrss (00) is b0, measure the pulse width vpw2 of pin 22 (vd1-out) wave form. (4) when sub-addrss (00) is 30, 70, f0, measure the pulse width vpw0, vpw1, vpw3 of pin 22 (vd1-out) wave form as well. vpw * signal a 29.63 s 0.593 s pin 22 wave form v period
TA1318N 2003-02-19 35 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) va04 vertical free-run frequency c b ? ? (1) input signal a (horizontal 33.75 khz) to pin 11 (hd3-in). (2) set sub-address (00) b0. (3) when sub-address (02) is 02, 22, 62, 82, a2 or c2, measure the frequency fv0, fv1, fv3, fv4, fv5 or fv6 of pin 22 (vd1-out) wave form. (4) input no-signal to pin 3 (hd1-in). (5) set sub-address (02) 42. (6) when sub-address (00) is 30, 70, b0 or f0, measure the frequency fv20, fv21, fv22 or fv23 of pin 22 (vd1-out) wave form. 0.285 v vpw * signal a 29.63 s 0.593 s pin 22 wave form v period
TA1318N 2003-02-19 36 sw mode note item s06 s18 s19 s21 test conditions and measuring method (v cc = 9 v, ta = 25 3 c, unless otherwise specified) va05 vertical pull-in range c b ? ? (1) input signal a (horizontal period t = 63.5 s) to pin 11 (hd3-in). (2) set sub-address (02) 02. (3) set sub-address (00) 30. (4) input signal c (vertical period initial t = 1ms) to pin 10 (vd3-in). increasing vertical period of signal c, measure the frequency fvpl0 when pin 22 (vd1-out) wave form synchronize with signal c. (5) input signal a (horizontal period t = 31.75 s) to pin 11 (hd3-in). (6) set sub-address (00) 70. (7) measure fvpl1 as well. (8) input signal a (horizontal period t = 29.63 s) to pin 11 (hd3-in). (9) set sub-address (00) b0. (10) measure fvpl2 as well. (11) input signal a (horizontal period t = 22.22 s) to pin 11 (hd3-in). (12) set sub-address (00) f0. (13) measure fvpl3 as well. 1.5 v signal a horizontal period t s 0.593 s signal c v period (initial t = 1 ms) 1.5 v 0.25 ms pin 22 wave form measuring period
TA1318N 2003-02-19 37 test circuit m 0.01 f 100 ? pin 9 #9 100 ? pin 10 #10 100 ? pin 11 #11 100 ? pin 12 #12 100 ? pin 1 #1 100 ? pin 2 #2 100 ? pin 3 #3 100 ? pin 4 #4 pin 6 #6 360 ? #7 1 k ? 10 k ? 68 k ? 7.5 k ? pin 7 csbla503 keczf30 sw6 a b c 2.2 f 0.01 f 100 f 10 k ? #24 5.1 k ? #23 5.1 k ? #22 5.1 k ? #15 100 ? scl #17 100 ? sda #16 100 ? pin 20 #20 5.1 k ? #13 #21 1 f a b sw21 sync1 #19 1 f a b sw19 sync2 sw18 a b c 0.01 f #18 100 f 0.01 f 100 f 0.01 f reg. 9 v 5 v 9 v 100 f 0.01 f 1 k ? 1 k ? 5.1 k ? 5.1 k ? 75 ? 75 ? 10 f 10 f 3.9 k ? 3.9 k ? tp s 1-in tp s 2-in 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 dac3 vd2-out vd1-out sync1-in dac1 sync2-in address sw scl sd a hd2-out digital gnd hd1-out hd2-in vd2-in hd1-in vd1-in analog gnd afc filter hvco v cc dac2 vd3-in hd3-in cp-out TA1318N m mylar capacitor
TA1318N 2003-02-19 38 application circuit 1 (typical values) m 0.01 f dac2 vd3-in hd3-in cp-out hd2-in vd2-in hd1-in vd1-in 7.5 k ? csbla503 keczf30 2.2 f 15 k ? dac3 10 k ? 10 k ? 10 k ? 100 ? scl 100 ? sda dac1 10 k ? 1 f sync1- in 1 f sync2- in 100 f 0.01 f 9 v 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 dac3 vd2-out vd1-out sync1-in dac1 sync2-in address sw scl sd a hd2-out digital gnd hd1-out hd2-in vd2-in hd1-in vd1-in analog gnd afc filter hvco v cc dac2 vd3-in hd3-in cp-out TA1318N m mylar capacitor vd2- out vd1- out hd2- out hd1- out 360 ? 0.01 f 100 f
TA1318N 2003-02-19 39 application circuit 2 (how to measure h/v frequency) to measure h/v frequency of signal 2 (fh2: unknown) correctly, use two separated input terminals as the following figure. one is for frequency measuring (sync2-in) and the other is for the afc (sync1-in). and measure h/v frequency of signal 2 (fh2: unknown) on condition that afc is stable (afc locks in signal 1 (fh1: known).) or that afc is free-run when sync1-in is no-signal. this ic?s h/v frequency counting is done by internal pulse (a) which is made in afc circuit. so, if afc circuit doesn?t lock in the regular frequency, the frequency of pulse (a) will not be correct and the h/v frequency data will not be showed correct data. decision algorithm of h/v frequency detection (detection range, detection times and so on) should be determined under consideration the factors such as signal strength, existence of ghost signal, h-afc stability, i 2 c bus data transmission and so on via prototype tv set evaluation. h/v freq counter afc internal pulse (a) signal 1 signal 2 bus read signal 1 (fh1: known) signal 2 (fh2: unknown) sync1-in for h-afc sync2-in for h/v freq. counter TA1318N
TA1318N 2003-02-19 40 package dimensions weight: 1.22 g (typ.)
TA1318N 2003-02-19 41 ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer?s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. ? the information contained herein is subject to change without notice. 000707eb a restrictions on product use

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